View MCM56824A_155580.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MCM56824A/D
DSPRAMTM 8K x 24 Bit Fast Static RAM
The MCM56824A is a 196,608 bit static random access memory organized as 8,192 words of 24 bits. The device integrates an 8K x 24 SRAM core with multiple chip enable inputs, output enable, and an externally controlled single address pin multiplexer. These functions allow for direct connection to the Motorola DSP56001 Digital Signal Processor and provide a very efficient means for implementation of a reduced parts count system requiring no additional interface logic. The availability of multiple chip enable (E1 and E2) and output enable (G) inputs provides for greater system flexibility when multiple devices are used. With either chip enable input unasserted, the device will enter standby mode, useful in low-power applications. A single on-chip multiplexer selects A12 or X/Y as the highest order address input depending upon the state of the V/S control input. This feature allows one physical static RAM component to efficiently store program and vector or scalar operands by dynamically re-partitioning the RAM array. Typical applications will logically map vector operands into upper memory with scalar operands being stored in lower memory. By connecting DSP56001address A15 to the VECTOR/SCALAR (V/S) MUX control pin, such partitioning can occur with no additional components. This allows efficient utilization of the RAM resource irrespective of operand DQ0 type. See application diagrams at the end of this document for additionDQ1 al information. DQ2 Multiple power and ground pins have been utilized to minimize effects VSS induced by output noise. DQ3 The MCM56824A is available in a 52 pin plastic leaded chip-carrier DQ4 (PLCC) and a 9 x 10 grid, 86 bump surface mount PBGA. DQ5 * * * * * * * * * * Single 5 V 10% Power Supply Fast Access and Cycle Times: 20/25/35 ns Max Fully Static Read and Write Operations Equal Address and Chip Enable Access Times Single Bit On-Chip Address Multiplexer Active High and Active Low Chip Enable Inputs Output Enable Controlled Three State Outputs High Board Density PLCC Package Low Power Standby Mode Fully TTL Compatible PIN NAMES
A0 - A11 . . . . . . . . . . . . . . . Address Inputs A12, X/Y . . . . . . . . . . Multiplexed Address V/S . . . . . . . . . Address Multiplexer Control W . . . . . . . . . . . . . . . . . . . . . . . Write Enable E1, E2 . . . . . . . . . . . . . . . . . . . Chip Enable G . . . . . . . . . . . . . . . . . . . . . . Output Enable DQ0 - DQ23 . . . . . . . . . . Data Input/Output VCC . . . . . . . . . . . . . . . +5 V Power Supply VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground NC . . . . . . . . . . . . . . . . . . . . No Connection For proper operation of the device, all VSS pins must be connected to ground. DQ6 DQ7 DQ8 VSS DQ9 DQ10
MCM56824A
FN PACKAGE 52-LEAD PLCC CASE 778-02
9 x 10 GRID 86 BUMP PBGA CASE 896A-01
PIN ASSIGNMENTS
PLCC A10 A11 A12 X/Y V/S NC V CC A0 A1 A2 A3 A4 A5 7 6 5 4 3 2 1 52 51 50 49 48 47 46 8 45 9 44 10 43 11 42 12 41 13 40 14 39 15 38 16 37 17 36 18 35 19 20 21 22 23 24 25 26 27 28 29 30 31 32 3334 DQ11 A9 A8 A7 A6 G VCC VSS E1 E2 W NC DQ12 10 VIEW OF PBGA PACKAGE BOTTOM 9 8 7 6 5 4 3 2 DQ23 DQ22 DQ21 VSS DQ20 DQ19 DQ18 DQ17 DQ16 DQ15 VSS DQ14 DQ13
1
A B C D E F G H J W E1 VSS VCC G A7 A9
D13 VSS D12 D14 E2 VSS
D16 D17 D18 D20 D21 D23 D15 D19 VSS D22 A5 A3 A1 A4 A2 A0 VCC
A6 A8 D11 D9 D8 D7 D6 D4 D5 VSS D3 D1 D2
V/S NC A12 X/Y A10 A11 D0
D10 VSS
DSPRAM is a trademark of Motorola, Inc.
REV 2 4/95
Not to Scale
(c) Motorola, Inc. 1995 MOTOROLA FAST SRAM
MCM56824A 1
BLOCK DIAGRAM
V/S X/Y A12 A0
* * *
A12 1 Q 0 2 TO 1 MUX MEMORY ARRAY ROW DECODER
* * *
VCC VSS
A5 A10 A11
512 ROWS x 384 COLUMNS
***
DQ0
* * *
DQ23 E1 E2 W G
INPUT DATA CONTROL
* * *
COLUMN I/O
* * *
COLUMN DECODER
***
A6 (LSB) (MSB)
A9
TRUTH TABLE
E1 H X L L L L L E2 X L H H H H H G X X H L L X X W X X H H H L L V/S X X X H L H L Mode Not Selected Not Selected Output Disable Read Using X/Y Read Using A12 Write Using X/Y Write Using A12 Supply Current ISB ISB ICC ICC ICC ICC ICC I/O Status High-Z High-Z High-Z Data Out Data Out Data In Data In
NOTE: X=don't care.
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = 0 V)
Rating Power Supply Voltage Voltage Relative to VSS for Any Pin Except VCC Output Current (per I/O) Power Dissipation Temperature Under Bias Operating Temperature Storage Temperature Symbol VCC Vin, Vout Iout PD Tbias TA Tstg Value - 0.5 to + 7.0 - 0.5 to VCC + 0.5 20 1.75 - 10 to + 85 0 to + 70 - 55 to + 125 Unit V V mA W C C C This device contains circuitry to protect against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is assumed to be in a test socket or mounted on a printed circuit board with at least 300 LFPM of transverse air flow being maintained.
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
MCM56824A 2
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 10%, TA = 0 to + 70C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (Voltages Referenced to VSS = 0 V)
Parameter Supply Voltage (Operating Voltage Range) Input High Voltage Input Low Voltage * VIL (min) = - 3.0 V ac (pulse width 20 ns) Symbol VCC VIH VIL Min 4.5 2.2 - 0.5* Typ 5.0 -- -- Max 5.5
VCC + 0.3
Unit V V V
0.8
DC CHARACTERISTICS
Parameter Input Leakage Current (All Inputs, Vin = 0 to VCC) Output Leakage Current (G = VIH, E1 = VIH, E2 = VIL, Vout = 0 to VCC) AC Supply Current (G = VIH, E1 = VIL, E2 = VIH, Iout = 0 mA, All Other Inputs VIL = 0.0 V and VIH 3.0 V) MCM56824A-20 Cycle Time: 20 ns MCM56824A-25 Cycle Time: 25 ns MCM56824A-35 Cycle Time: 35 ns Standby Current (E1 = VIH, E2 = VIL, All Inputs = VIL or VIH) CMOS Standby Current (E1 VCC - 0.2 V, E2 0.2 V, All Inputs VCC - 0.2 V or 0.2 V) Output Low Voltage (IOL = + 8.0 mA) Output High Voltage (IOH = - 4.0 mA) Symbol Ilkg(i) Ilkg(O) ICCA -- -- -- ISB1 ISB2 VOL VOH -- -- -- 2.4 260 220 180 15 10 0.4 -- mA mA V V Min -- -- Max 1.0 1.0 Unit A A mA
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25C, Periodically Sampled Rather Than 100% Tested)
Parameter Input Capacitance Input/Output Capacitance All Pins Except DQ0 - DQ23 DQ0 - DQ23 Symbol Cin Cout Typ 4 6 Max 6 8 Unit pF pF
+5V RL = 50 OUTPUT Z0 = 50 VL = 1.5 V 480 OUTPUT 255 5 pF
(a)
(b)
Figure 1. AC Test Loads
MOTOROLA FAST SRAM
MCM56824A 3
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 10%, TA = 0 to + 70C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . See Figure 1a Unless Otherwise Noted
READ CYCLE TIMING (See Notes 1, 2, and 3)
MCM56824A-20 Parameter Read Cycle Time Address Access Time MUX Control Valid to Output Valid Chip Enable to Output Valid Output Enable to Output Valid Output Active from Chip Enable Output Active from Output Enable Output Hold from Address Change Output Hold from MUX Control Change Chip Enable to Output High-Z Symbol tAVAV tAVQV tVSVQV tE1LQV tE2HQV tGLQV tE1LQX tE2HQX tGLQX tAXQX tVSXQX tE1HQZ tE2LQZ Min 20 -- -- -- -- 2 0 4 4 0 Max -- 20 20 20 8 -- -- -- -- 10 MCM56824A-25 Min 25 -- -- -- -- 2 0 5 5 0 Max -- 25 25 25 10 -- -- -- -- 15 MCM56824A-35 Min 35 -- -- -- -- 0 0 5 5 0 Max -- 35 35 35 15 -- -- -- -- 15 Unit ns ns ns ns ns ns ns ns ns ns 4, 5 4, 5 5 4 Notes
Output Enable High to Output High-Z tGHQZ 0 8 0 15 0 15 ns 5 NOTES: 1. A read cycle is defined by W high. 2. All read cycle timings are referenced from the last valid address or vector/scalar transition to the first address or vector/scalar transition. 3. Addresses valid prior to or coincident with E1 going low or E2 going high. 4. E1 in the timing diagrams represents both E1 and E2 with E1 asserted low and E2 asserted high. 5. Transition is measured 500 mV from steady-state voltage with load of Figure 1b. This parameter is sampled and not 100% tested. At any given voltage and temperature, tE1HQZ max is less than tE1LQX min, tE2LQZ max is less than tE2HQX min, and tGHQZ max is less than tGLQX min for a given device and from device to device.
READ CYCLE
tAVAV A (ADDRESS) tAVQV V/S (MUX CONTROL) tVSVQV E1 (CHIP ENABLE) tE1LQV tGLQV G (OUTPUT ENABLE) tGLQX Q (DATA OUT) HIGH-Z tE1LQX tGHQZ DATA VALID HIGH-Z tE1HQZ tVSXQX tAXQX
MCM56824A 4
MOTOROLA FAST SRAM
WRITE CYCLE TIMING (Write Enable Initiated, See Note 1)
MCM56824A-20 Parameter Write Cycle Time Address Setup Time MUX Control Setup Time Address Valid to End of Write MUX Control Valid to End of Write Write Pulse Width Write Enable to Chip Enable Disable Chip Enable to End of Write Data Valid to End of Write Data Hold Time Write Recovery Time MUX Control Recovery Time Write High to Output Low-Z Symbol tAVAV tAVWL tVSVWL tAVWH tVSVWH tWLWH tWLE1H tWLE2L tE1LWH tE2HWH tDVWH tWHDX tWHAX tWHVSX tWHQX Min 20 0 0 15 15 15 15 15 8 0 0 0 4 Max -- -- -- -- -- -- -- -- -- -- -- -- -- MCM56824A-25 Min 25 0 0 20 20 15 15 15 10 0 0 0 5 Max -- -- -- -- -- -- -- -- -- -- -- -- -- MCM56824A-35 Min 35 0 0 30 30 20 20 20 15 0 0 0 5 Max -- -- -- -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 6 5 2 3 3, 4 3, 4 2 Notes
Write Low to Output High-Z tWLQZ 0 15 0 15 0 15 ns 6 NOTES: 1. A write cycle starts at the latest transition of E1 low, W low, or E2 high. A write cycle ends at the earliest transition of E1 high, W high, or E2 low. 2. Write must be high for all address transitions. 3. If W goes low coincident with or prior to E1 low or E2 high the outputs will remain in a high-impedance state. 4. E1 in the timing diagrams represents both E1 and E2 with E1 asserted low and E2 asserted high. 5. During this time the output pins may be in the output state. Signals of opposite phase must not be applied to the outputs at this time. 6. Transition is measured 500 mV from steady-state voltage with load of Figure 1b. This parameter is sampled and not 100% tested. At any given voltage and temperature, tE1HQZ max is less than tE1LQX min, tE2LQZ max is less than tE2HQX min, and tGHQZ max is less than tGLQX min for a given device and from device to device.
WE INITIATED WRITE CYCLE
tAVAV A (ADDRESS) tAVWH V/S (MUX CONTROL) tVSVWH tE1LWH E1 (CHIP ENABLE) tVSVWL W (WRITE ENABLE) tAVWL tDVWH D (DATA IN) tWLQZ Q (DATA OUT) HIGH-Z HIGH-Z tWLE1H tWHDX tWLWH tWHVSX tWHAX
VALID DATA IN tWHQX
MOTOROLA FAST SRAM
MCM56824A 5
WRITE CYCLE TIMING (Chip Enable Initiated, See Note 1)
MCM56824A-20 Parameter Write Cycle Time Address Setup Time MUX Control Setup Time Address Valid to End of Write MUX Control Valid to End of Write Chip Enable to End of Write Data Valid to End of Write Data Hold Time Write Recovery Time MUX Control Recovery Time Symbol tAVAV tAVE1L tAVE2H tVSVE1L tVSVE2H tAVE1H tAVE2L tVSVE1H tVSVE2L tE1LE1H tE2HE2L tDVE1H tDVE2L tE1HDX tE2LDX tE1HAX tE2LAX tE1HVSX tE2LVSX Min 20 0 0 15 15 12 8 0 0 0 Max -- -- -- -- -- -- -- -- -- -- MCM56824A-25 Min 25 0 0 20 20 15 10 0 0 0 Max -- -- -- -- -- -- -- -- -- -- MCM56824A-35 Min 35 0 0 30 30 20 15 0 0 0 Max -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns 2 2 2 2 2, 3 2 2, 4 2 2 Notes
NOTES: 1. A write cycle starts at the latest transition of E1 low, W low, or E2 high. A write cycle ends at the earliest transition of E1 high, W high, or E2 low. 2. E1 in the timing diagrams represents both E1 and E2 with E1 asserted low and E2 asserted high. 3. If W goes low coincident with or prior to E1 low or E2 high the outputs will remain in a high-impedance state. 4. During this time the output pins may be in the output state. Signals of opposite phase must not be applied to the outputs at this time.
E1 OR E2 INITIATED WRITE CYCLE
tAVAV A (ADDRESS) tAVE1H V/S (MUX CONTROL) tVSVE1H E1 (CHIP ENABLE) W (WRITE ENABLE) tE1LE1H tAVE1L tVSVE1L tDVE1H D (DATA IN) DATA VALID tE1HDX tE1HVSX tE1HAX
Q (DATA OUT)
HIGH-Z
MCM56824A 6
MOTOROLA FAST SRAM
DSPRAM Multiplexed Vector/Scalar Address Maps
DSP56001 MCM56824A
8K x 24 DSPRAM Used in Typical Application
DSP56001 D0 - D23 MCM56824A D0 - D23 A0 - A11 A12 V/S X/Y MEMORY MANAGEMENT PINS
A0 - A11 A12 X/Y V/S
A0 - A11 MUX RAM A12
A0 - A11 A12 A15 X/Y
WR
W
4K x 24 "X" OPERANDS PROGRAM MEMORY HIGH 4K x 24 "Y" OPERANDS PROGRAM MEMORY LOW V/S = "1" PROGRAM MEMORY V/S = "0" 8K x 24 "X" OPERANDS
ORDERING INFORMATION
(Order by Full Part Number) MCM
Motorola Memory Prefix Shipping Method (R2 = Tape and Reel, Blank = rails) Part Number Speed (20 = 20 ns, 25 = 25 ns, 35 = 35 ns) Package (FN = PLCC, ZP = PBGA) Full Part Numbers -- MCM56824AFN20 MCM56824AFN25 MCM56824AFN35 MCM56824AZP20 MCM56824AZP25 MCM56824AZP35 MCM56824AZP20R2 MCM56824AZP25R2 MCM56824AZP35R2
56824A
XX
XX XX
MOTOROLA FAST SRAM
MCM56824A 7
PACKAGE DIMENSIONS
ZP PACKAGE 9 x 10 PBGA CASE 896A-01
0.20 (0.008)
B -B-
-T10 A B C D 9 8 7 6 5 4 3 2 1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. DIM A B C D G L N R MILLIMETERS MIN MAX 16.36 16.16 17.88 17.68 1.73 1.33 0.81 0.69 1.524 BSC 2.44 1.84 14.20 13.80 15.69 15.29 INCHES MIN MAX 0.637 0.644 0.697 0.703 0.053 0.068 0.028 0.031 0.060 BSC 0.073 0.096 0.544 0.559 0.602 0.617
G
A
N
E F G H J
R
C L
G
D 86 PL
-A-
0.50 (0.020)
M
TB
S
A
S
MCM56824A 8
MOTOROLA FAST SRAM
FN PACKAGE 52-LEAD PLCC CASE 778-02
-N-
Y BRK D
B U
0.18(0.007)
M
TN
M
S
-P
S S
L -P
S S
-M L
S S
0.18(0.007)
TN
-M
S
-L-
52 LEADS ACTUAL
-MW D V A 0.25(0.010)
S
NOTE 1 Z1
(NOTE 1) 52 -P-
1
G1 T L
S
-M
S
N
S
-P
S
VIEW D-D
0.25(0.010)
S
TN
S
-P
S
L
S
-M
S
Z R 0.25(0.010)
S
T
L
S
-M
S
N
S
-P
S
X
H
0.18(0.007) 0.18(0.007)
M M
TL TN
S S
-M -P
S S
N L
S S
-P -M
S S
C 52 (NOTE 1)
K1 E 0.10 (0.004) G G 1 TL J -TSEATING PLANE
K F DETAIL S 0.18(0.007) 0.18(0.007)
M M
DETAIL S
DIM A B C E F G H J K R U V W X Y Z G1 K1 Z1 MILLIMETERS MIN MAX 19.94 20.19 19.94 20.19 4.57 4.20 2.79 2.29 0.48 0.33 1.27 BSC 0.81 0.66 -- 0.51 -- 0.64 19.05 19.20 19.05 19.20 1.21 1.07 1.21 1.07 1.42 1.07 0.50 -- 10 2 18.04 18.54 1.02 -- 2 10 INCHES MIN MAX 0.785 0.795 0.785 0.795 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 -- 0.025 -- 0.750 0.756 0.750 0.756 0.042 0.048 0.042 0.048 0.042 0.056 -- 0.020 2 10 0.710 0.730 0.040 -- 2 10
TL TN
S S
-M -P
S S
N L
S S
-P -M
S S
0.25(0.010)
S
S
-M
S
N
S
-P
S
NOTES: 1. DUE TO SPACE LIMITATION, CASE 778-02 SHALL BE REPRESENTED BY A GENERAL (SMALLER) CASE OUTLINE DRAWING RATHER THAN SHOWING ALL 52 LEADS. 2. DATUMS -L-, -M-, -N-, AND -P- DETERMINED WHERE TOP OF LEAD SHOULDER EXIT PLASTIC BODY AT MOLD PARTING LINE. 3. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 4. DIM R AND U DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTRUSION IS 0.25 (0.010) PER SIDE. 5. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 6. CONTROLLING DIMENSION: INCH.
MOTOROLA FAST SRAM
MCM56824A 9
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 303-675-2140 or 1-800-441-2447 JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. 81-3-5487-8488
MfaxTM: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, - US & Canada ONLY 1-800-774-1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 INTERNET: http://motorola.com/sps
MCM56824A 10
MCM56824A/D MOTOROLA FAST SRAM

▲Up To Search▲

Price & Availability of MCM56824A

	To Download MCM56824A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .